Images

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Portraits

• Stephan Bökelmann – Portrait 2020 Stephan_Boekelmann_Avatar_2020.jpg
• Stephan Bökelmann – Portrait 2024 Stephan_Boekelmann_Avatar_2024.jpg
• Stephan Bökelmann – Comic Avatar Stephan_Boekelmann_Comic_Avatar.jpg
• Stephan Bökelmann – Kfz-Technik, Haltern 2010 Stephan_Boekelmann_Kfz-Technik_2010.jpg
• Stephan Bökelmann at CERN, 2018 Stephan_Boekelmann_at_CERN_2018.jpg
• Stephan Bökelmann – Business Portrait 2021 Stephan_Boekelmann_suit_2021.jpg

Counting Raindrops with a Capacitor: The 25square Sensor, Its STM32, and the Patent Behind It

• The 25square project team at the IUZ Sternwarte Bochum, where the first two sensors went into the ground in May… 25square-inline-3.jpg
• One of the sensors up close: the impact plate on its mast, the electronics in the sealed box below, PoE via the… 25square-sensor-impact-plate.jpg
• Tabea with one of the first installed sensors at the Sternwarte. 25square-sensor-sternwarte-bochum.jpg

ALINX AX7020, Stage 5 Complete: Cold Power-On to a Bitstream API, Nobody Logged In

• The ALINX AX7020 on the bench with the four PL LEDs blinking, the open-toolchain blinky loaded through the REST API blinky-running.gif

ALINX AX7020, Stages 4 & 5: An Open Bitstream Over REST, and the One Missing Line That Hangs Both Cores

• Swagger UI of the bitstream service, served by the AX7020 itself api-swagger-ax7020.png

ALINX AX7020 Bring-up: Mainline U-Boot Over JTAG, No FSBL, No Serial Cable

• Boot-mode header J13 with the jumper on the JTAG position boot-mode-jumper-jtag.jpg
• Boot-mode header J13 with the jumper on the QSPI position boot-mode-jumper-qspi.jpg
• EMC lab test of the jointly specified cables with Auto-Intern's new edge-compute hardware emc-lab-test.jpg
• Visiting the GH Electronic team in Dongguan gh-factory-visit.jpg
• Cable production floor at GH Electronic gh-production.jpg
• Auto-Intern M12 Ethernet adapter connected to the ALINX AX7020 m12-adapter.jpg

ALINX AX7020 — The Open Bitstream Pipeline Series

• ALINX AX7020 on the bench: Zynq XC7Z020 in the centre, boot jumper J13 on JTAG, Ethernet and JTAG attached ax7020-board.jpg
• ALINX AX7020 Zynq-7020 board powered up (thumbnail) ax7020-board-thumb.jpg

A Hill I Am Willing to Die On: HDL for PCB Netlists

• PCB layout view showing dense copper routing, vias, and component placement: a constraint-satisfaction problem of a… routing.png
• A dense KiCad schematic with multiple Ethernet PHY blocks, bypass capacitors, and interconnected nets: the kind of… titlepic.png

KiCon Europe 2026: Trip Report without the Trip

• Selfie in the main hall of Gleis 9 with the KiCon Europe 2026 audience behind me audience-selfie.jpg
• cpresser on stage with his one-page Design a Circuit Board with KiCad handout on the screen cpresser-workshop-talk.jpg
• Magnus Axelsson and Simon Lindh from EUB on stage with a red 3D-printed test rig on the lectern eub-test-rig.jpg
• Lunch break in the covered courtyard of Gleis 9 with deck chairs and the Würth Elektronik stand lunch-courtyard-gleis9.jpg
• Raphael Specht of Würth Elektronik presenting KiCad 3D models raphael-specht-wuerth-3d-models.jpg
• Seth Hillbrand at the registration and merchandise desk at the Gleis 9 bar registration-desk.jpg
• Yellow crate labelled KiCon on top of boxes of thermos pots in the storage room storage-crates.jpg
• Storage shelf with mugs, glasses and flight cases after the conference storage-shelf.jpg
• Training day at Gleis 9: attendees at laptops following Seth Hillbrand through a KiCad schematic workshop-seth-day3.jpg
• Seth Hillbrand at the lectern with the KiCad schematic editor on the screen workshop-seth-lectern.jpg

Why Does Copper Conduct? A Tour for Non-Physicists

• From two atoms to N atoms: levels merge into bands fig_band_formation.png
• Metal, semiconductor, insulator in the band picture fig_band_types.png
• Bonding and antibonding states of two coupled atoms fig_bonding_antibonding_nodes.png
• Discrete energy levels of a single atom fig_atom_levels.png

Physics, Math, or Engineering? How do you decide

• Three figures around a boulder in the mountains: a physicist with equations, a mathematician at a chalkboard, an… titlepic.jpg

What AI Actually Is

• Two plots side by side. Left: three training points with a parabola fitting them perfectly. Right: the same three… interpolation-vs-extrapolation.png

WTF are FPGAs: A Beginner's Overview of Field-Programmable Gate Arrays

• A Lattice iCEstick USB dongle next to a Digilent Basys3 development board: two ends of the FPGA beginner spectrum,… basys3-icestick-title.jpg
• FPGA architecture diagram showing a grid of orange Logic Blocks connected by a Programmable Interconnect fabric,… fpga-architecture-diagram.png
• Two Xilinx Kintex-7 development boards connected to an oscilloscope for post-implementation signal verification,… kintex7-oszi.jpg
• A Xilinx Kintex-7 evaluation board in PCIe form factor, with two Panda FMC mezzanine cards attached, an SFP cage,… kintex7-pcie.jpg
• Vivado simulation waveform: signal list on the left, time-domain traces on the right. State machine signals, AXI4… vivado-sim.png

If We Can Measure It, You Can Improve It

• Four people in a VW bus on the way to somewhere that matters intro-bild.jpg

Travelling to China with a Peli Case Full of Electronics

• Peli case packed: foam cut to fit, modules secured, cables coiled alongside photo_1_2026-04-14_16-02-16.jpg
• TSA-compliant lock — one of two on the case. One didn't make it back. photo_2_2026-04-14_16-02-16.jpg
• Black Peli hard case for the ATA Carnet equipment photo_5_2026-04-14_14-19-10.jpg

How Two Teenagers, a Printer Plug, and a Forum Post Built a Company

• AutoSpion — front view AutoSpion.jpg
• AutoSpion — rear view AutoSpionBack.jpg
• HEX-V2 interface — current product HEX-V2.jpg
• Auto-Intern Multiscan USB Multiscan.jpg
• The V.A.G 1551 — the factory diagnostic tool that started it all VAG1551.jpg
• VCDS main menu VCDS-Screenshot_1_2026-05-06_11-34-03.jpg
• VCDS — ECU identification screen VCDS-Screenshot_2_2026-05-06_11-34-03.jpg
• VCDS — long coding with bit-level editor VCDS-Screenshot_5_2026-05-06_11-34-03.jpg
• VCDS — fault memory readout VCDS-Screenshot_3_2026-05-06_11-34-03.jpg
• VCDS — extended live data VCDS-Screenshot_4_2026-05-06_11-34-03.jpg

EMC in Dongguan: 2.5 Years of Work, 4 Days in a Test Chamber

• Stopover in Shenzhen — the trip begins photo_1_2026-04-14_14-19-10.jpg
• Setup in progress — the NTC technician preparing the conducted immunity test photo_2_2026-04-14_14-19-10.jpg
• Top-down view of the test arrangement photo_3_2026-04-14_14-19-10.jpg
• Inside the anechoic chamber — radiated emissions test in progress photo_4_2026-04-14_14-19-10.jpg
• Everything packed into a Peli case for the flight to Dongguan photo_5_2026-04-14_14-19-10.jpg
• Full test bench at NTC — compute module, sensor nodes, M12 PoE cables, ThinkPad for monitoring photo_7_2026-04-14_14-19-10.jpg

Dual Uplink for 15 People: Starlink, Heimdall, and Linux Routing

• Setup workspace in the basement — AI-heimdall in the mini-rack on the right, terminal output on the monitor PXL_20260306_175202894.jpg
• `ip a` on AI-heimdall — eno1 (DSL), eno2 (Starlink), and eno4 (internal network) all active PXL_20260306_205143846.jpg

Enclosureless Cases: When the PCB Is the Enclosure

• Enclosureless Cases components and assembled unit — bottom board, frame spacer, cover board, and the finished sensor photo_enclosureless_temphumid.jpg

Zero to One: VHDL and a Lattice iCEstick

• GTKWave showing tb_blinky with dut selected in the SST tree and clk, counter, led_reg visible in the wave view gtkwave.png
• iCEstick leaning against a Ruhr-Universität Bochum physics department mug, mixer and monitor in the background titlepic.jpg

The Game of Life and the Limits of Prediction

• Conway's Game of Life — structures evolving on a grid GoL-Opener.png
• Boltzmann — Thermodynamics and Statistical Mechanics statistical-mechanics.png

Getting Started: From Tape-Out to TypeScript

• Stephan Bökelmann at CERN, Geneva — accelerator pipe reading "Accelerating Science" title.jpg

Bonding verification station in the lab: a monitor with the readout software on top of a rack crate, next to a green test PCB carrying a freshly wire-bonded sensor chip. By Stephan Bökelmann (MaxClerkwell).

• Bonding verification station with readout crate and test PCB Bonding-Verification-Station.jpg
• The SIS100 tunnel at FAIR, Darmstadt — superconducting dipole magnets installed, connection pipes between magnets… SIS100.jpg
• Bare HV-MAPS silicon chips in a waffle pack chips.jpg
• Python surface plots of the HESR parameter sweep — MPV deposited energy, mean deposited energy, and e/h pairs at MPV… first-try-antiproton.jpg
• The Geant4 Qt GUI running exampleB1 — 3D geometry viewer on the right, command tree on the left, output log at the… geant-exampleB1.jpg
• Stephan Bökelmann in front of the PROTON supermarket, sign circled me-being-anti-proton (Edited).jpg
• Stephan Bökelmann a.k.a MaxClerkwell and another researcher from RUB standing in a supermarket parking lot on Corfu… me-being-anti-proton.jpg
• MuPix8 evaluation board mounted in the COSY test beam setup, 2022 mupix-8-beamtime.jpg

KiCon Asia 2025: Speaking on Wire Bonding in Shenzhen

• KiCon 2025 Asia conference programme banner photo_1_2026-04-15_13-23-32.jpg
• Another speaker presenting on the LLM ecosystem — the scale of the screens was something photo_2_2026-04-15_13-23-32.jpg
• Shenzhen night skyline — the twin towers near the venue photo_3_2026-04-15_13-23-08.jpg
• The prize koala, sitting on the KiCad × Huaqiu conference folder photo_4_2026-04-15_13-23-32.jpg
• Dell laptop showing wire bonding slides — CLICpix and MuPix microscope images photo_5_2026-04-15_13-23-32.jpg
• Shenzhen street scene — daytime, near the conference area photo_6_2026-04-15_13-23-32.jpg
• Stephan in Shenzhen — obligatory selfie with the skyline photo_7_2026-04-15_13-23-32.jpg
• Presenting at KiCon Asia 2025 — CLICpix microscope image on screen behind photo_8_2026-04-15_13-23-32.jpg

KiCon Europe 2024: Bochum Goes International

• Pre-conference social the evening before — group dinner at a traditional Bochum pub PXL_20240918_182811826.jpg
• The Rotunde the evening before doors open — standing tables set up, venue empty PXL_20240918_192310290.jpg
• Lukas Hartmann presenting on open hardware CPU modules at KiCon Europe 2024 PXL_20240919_072728340.MP.jpg
• Odin Holmes on stage at KiCon Europe 2024 — Edgy talk PXL_20240920_070542079.MP.jpg

Are Machines Conscious? A Snapshot

• Are Machines Conscious? title1.jpg

Biofilms in Rivers: EIS at the Clark Fork

• Tabea Bökelmann on the MSU campus — Bronze Bobcat in the background, first day in Bozeman PXL_20240902_154058745.MP.jpg
• Final preparations in Prof. Warnat's lab the day before deployment PXL_20240903_190205585.jpg
• The rented Ram Rebel — transport for the deployment equipment PXL_20240904_133642042.jpg
• Deployment team at the Clark Fork site — bridge crossing, canopy tent, and a lot of cable PXL_20240904_160651813.jpg
• The sensor housing: PVC tube with the EIS electrode chip and flow apertures PXL_20240904_164739822.jpg
• Running cable from the bridge to the measurement hut PXL_20240904_164825527.MP.jpg
• Installing the sensor array at the riverbank — just below the bridge footing PXL_20240904_165019636.MP.jpg
• Field command centre — reviewing progress under the canopy PXL_20240904_172602699.MP.jpg
• Commissioning the datalogger software inside the measurement hut — first live EIS data from the Clark Fork PXL_20240904_192645256.jpg

OmnAIScope: A USB Oscilloscope for Automotive Diagnostics

• Data-server architecture: oscilloscope → local server → REST/WebSocket → analysis services architecture.png
• Demo setup at an automotive trade show — four scopes, a laptop, the Messkit 153 case demosetup.jpg
• Four OmnAIScope prototypes — BNC input on top, USB-C on the bottom early_prototype.jpg
• OmnAIScope complete kit — scope, BNC adapter, USB cable, probe, and accessories in carry case omnaiscope-kit.jpg
• OmnAIScope USB oscilloscope with BNC probe cable — red anodised aluminium housing omnaiscope-retail.jpg
• PCB, BNC connector, and housing — the three components before assembly photo_2026-04-14_16-25-24.jpg

PDSC4K 2026: Everything, Everywhere, All at Once

• The four zones of a real data pipeline — acquisition, warehousing, conditioning, and distribution architecture.png
• Real systems and real data – one of the practical examples on display gemesys.jpg
• Delivering the keynote at PDSC4K – four zones, one responsibility per box keynote-me-on-stage.jpg
• Last of the last – conversations still going strong on the rooftop last-of-the-last.jpg
• Lukas Jakubczyk presenting motor vibration analysis at PDSC4K lukas-jakubczyk-motor-vibration-analysis.jpg
• Lunch and the conversations that actually move projects forward lunch.jpg
• The four zones of a real data pipeline — acquisition, warehousing, conditioning, and distribution slides-english-architecture.png
• Selfie in the lab with a row of tower PCs forming a Ceph cluster slides-english-ceph.png
• horus monitoring PoE gateway in red aluminium housing slides-english-horus.png

Ten Years of PowerSense: Blood, Sweat, and Ferrite Cores

• Three generations of housing (left to right: early black prototype, tall white variant, final grey enclosure with… photo_1_2026-04-21_12-42-49.jpg
• Custom-developed PoE infrastructure for the switching stations: QUINT POWER 48V supply feeding two DB ECG PoE8… photo_2_2026-04-21_12-42-49.jpg
• DIANA Edge Computer Gateway — DB-branded prototype of the rack-mount edge compute unit developed alongside the… photo_3_2026-04-21_12-42-49.jpg
• Two bare PCBs: the sensor antenna board (top) and the PoE main board with RJ45 connector (bottom) — before any… photo_4_2026-04-21_12-42-49.jpg
• Measured current waveforms for L1, L2, L3 against reference — phase angles 257°, 262°, 323°. Orange (measured) and… photo_1_2026-04-21_12-43-36.jpg
• B-field crosstalk between phases: L1→L1 at 100%, L1→L2 at 2.22%, L1→L3 at 0.34% — demonstrating excellent channel… photo_2_2026-04-21_12-43-36.jpg

Zero to One: Fun with SWD

• STM32F303K8 Nucleo-32 on the desk Title.jpg
• Telnet session screenshot screenshot.png

Ten Years of Conferences: What They're Actually For

• Bar social at code:dive, Wrocław — the evenings are the real conference 20190202_220352.jpg
• Early morning on the Kona waterfront — ISO C++ Committee meeting, February 2019 20190218_071328.jpg
• emBO++ social evening — the conversations here continue all the way through the programme IMG_20220531_220208.jpg
• GSI/FAIR campus in Darmstadt — PANDA collaboration meeting IMG_20220601_131444.jpg
• emBO++ 2023 — the conference back at full pace after the pandemic years IMG_20230324_092047.jpg
• A smaller OSF evening event — focused format, green lighting, engaged audience PXL_20231103_182701752.MP.jpg
• Inside a PANDA collaboration session — "a glimpse at the many experimental groups" PXL_20240411_144041411.MP.jpg
• KiCon Europe 2024, Rotunde Bochum — Lukas Hartmann on open hardware PXL_20240919_072728340.MP.jpg
• emBO++ 2025 — conferences have not fully recovered to pre-COVID numbers yet PXL_20250306_155554013.MP.jpg
• emBO++ 2026 — still running, still worth it PXL_20260320_082116266.MP.jpg
• With Bjarne Stroustrup — Kona, 2019 stephan_und_bjarne.png

ALINX AX7020, Stages 2 & 3: A Yocto Linux in QSPI Flash That Fetches Its Own Updates

• Key-only SSH login on the AX7020 ssh-login-ax7020.png

Portraits

• A decapped integrated circuit under the LM210S: the bond pads along the die edge, aluminium wires running off to the lea lm210s-die-bondwires.jpg
• The LINKMICRO LM210S on the bench, a relay board clamped to its stage, the 10.1-inch screen showing the board's passives lm210s-on-bench.jpg

open.cob.json: One File Between the Chip Designer and the PCB Designer

• Microscope view of a chip edge: a row of aluminium bond pads, each with a wedge bond and a thin wire leaving downward to bond-wires-on-pads.jpg
• cobedit with the demo chip loaded: canvas on the left showing die, bond fingers, wires, keepout and fiducials; toolbox o cobedit-screenshot.png
• A bare die glued onto a PCB, gold-colored top metal catching the light, with a fan of thin bond wires running from the c die-on-board.jpg
• A bonding plan from an earlier project: chip photo with pad names and signal descriptions, colored wire lines drawn on t legacy-bonding-plan.jpg

A Naive Comparator: Two NPNs, One PNP, and a SPICE Simulation to Prove It

• DC transfer plot of the transistor comparator: V_IN swept from 0 to 5 V on the x axis, voltages on the y axis. OUT (oran dc-transfer.png
• Three DC transfer curves of OUT versus V_IN for V_REF = 1 V (blue), 2.5 V (orange) and 4 V (green), each with a dotted v dc-vref-family.png
• KiCad schematic of the transistor comparator: two 2N3904 NPN transistors Q1 and Q2 share an emitter node TAIL that goes schematic.png
• Transient plot over 40 µs. V_IN (blue) is a pulse train between 2.3 V and 2.7 V with 10 µs high and 10 µs low, around a tran-pulse.png
• Two stacked transient plots over 3 ms. Top: V_IN (blue) is a 1 kHz sine between 0.5 V and 4.5 V around a dashed 2.5 V li tran-sine.png

Why a LUT Is Programmable: Twenty Transistors, Sixteen Functions

• GTKWave displaying the simulation of the two-input LUT: the stored table as a hexadecimal vector, the inputs A and B and gtkwave.png
• One 800 ns function window of the simulation, with the LUT configured as XOR: the four table bits, the two inputs steppi lut2.png