Article series · since August 2026
Deploying hardware like software,
on an ALINX AX7020
ALINX sent me a Zynq-7000 development board. Instead of following the vendor workflow, I am replacing every black box between power-on and a configured FPGA with something whose source I can read: mainline U-Boot instead of the FSBL, Yocto instead of PetaLinux, Yosys and nextpnr instead of Vivado, a sysfs node instead of a programming cable, and an HTTP endpoint instead of a person. Every stage is documented as it happens, failures included.
The board
The ALINX AX7020 is a compact Zynq-7000 board built around the XC7Z020: a dual-core Cortex-A9 processing system and an Artix-7 class FPGA fabric on one die. It is the kind of board a project like this needs: all four boot sources are jumper-selectable, the Ethernet port hangs off the processor side and works with an empty FPGA, and the reference design is public.
- XC7Z020-2CLG400: 2× Cortex-A9 at 766 MHz plus 85k logic cells of 7-series fabric, JTAG IDCODE
0x23727093 - 1 GiB DDR3: two MT41J256M16 on a 32-bit bus at 533 MHz
- 32 MiB QSPI flash: Winbond W25Q256, home of the maintenance Linux
- Gigabit Ethernet: PS GEM0 with an RTL8211E PHY, usable before any bitstream exists
- Boot from JTAG, QSPI or SD, selected by one jumper
- USB OTG, UART, SD, four PL LEDs, a PL oscillator at 50 MHz, and two 40-pin expansion headers
- Open reference design from ALINX, from which the DDR and pin initialisation data is extracted without starting Vivado
Full disclosure: the board is a sponsorship gift. ALINX has no say in what I write, and the series ignores most of their recommended workflow.
The series, in order
- 1 Deploying Hardware Like Software: A Bitstream Pipeline for the Zynq August 23, 2026 Alinx sent me an AX7020 board. Here is the plan: an open-source path from JTAG bring-up to a REST API that accepts a bitstream and loads it onto the FPGA, no vendor tools in the loop.
- 2 ALINX AX7020 Bring-up: Mainline U-Boot Over JTAG, No FSBL, No Serial Cable August 30, 2026 Stage 1 of the open bitstream pipeline: putting mainline U-Boot on an ALINX AX7020 over JTAG and Ethernet only: a clean walkthrough of what works, followed by the nine detours it took to find out.
- 3 ALINX AX7020, Stages 2 & 3: A Yocto Linux in QSPI Flash That Fetches Its Own Updates August 31, 2026 Stages 2 and 3 of the open bitstream pipeline: a self-built Yocto Linux for the ALINX AX7020, resident in QSPI flash, discoverable on the company network, key-only SSH: the walkthrough that works, followed by the nine detours it took to get there.
- 4 ALINX AX7020, Stages 4 & 5: An Open Bitstream Over REST, and the One Missing Line That Hangs Both Cores September 14, 2026 Stages 4 and 5 of the open bitstream pipeline: a Yosys/nextpnr bitstream loaded into the ALINX AX7020 through the kernel's FPGA manager, a kexec updater that finally runs, and a FastAPI service that accepts bitstreams over HTTP, all without a single vendor tool; then the detours, including a PL design that silently drowned both Cortex-A9 cores in FIQs.
Next up: the maintenance Linux in flash fetches the full image on its own, and that image brings the bitstream API up as a service. Cold power-on to a working REST endpoint, nobody logged in.
For board vendors
Want your board taken apart like this?
This series exists because a vendor sent a board and got out of the way. If you make development boards, modules or silicon and want an independent, public, warts-and-all bring-up of your hardware with open tools, mainline software and an engineering audience, send a few lines about the board and what you would like to see.